A logic gate (e.g., a NAND gate) is made of multiple transistors, and a Central Processing Unit (CPU) or Graphics Processing Unit (GPU) includes many logic gates to provide processing capability. For instance, a particular pipeline stage in a CPU may include combinational logic having multiple, cascaded logic gates that feed information to a next pipeline stage. Thus, each pipeline stage may include a very large number of transistors.
A conventional transistor is subject to a phenomenon called “leakage,” where current is consumed even though the transistor is not transitioning between states. Leakage is a result of a given transistor being disposed between two different voltages where the transistor has a finite amount of resistance—some amount of current inevitably flows. Thus, even when a transistor is held in an OFF state, it still conducts some amount of current. In aggregate over the millions of transistors in a CPU or GPU, leakage current can consume a significant portion of the overall device power.
For a given logic gate, the amount of leakage current attributable to that logic gate depends on the state of the gate at a particular time. Therefore, as time goes on and the clock goes through many cycles, the logic gate transitions through states, with some states responsible for more leakage than others. The same is true for combinational logic made of multiple logic gates. As the clock goes through many cycles, the combinational logic changes states too (where the state of the combinational logic is attributable to the individual states of the logic gates).
Some conventional systems employ clock gating, wherein combinational logic is idled by holding the clock signal to a one or a zero for a period of time. When a clock to a particular piece of combinational logic is gated in such a conventional system, the combinational logic preserves its state until the clock is un-gated. However, the combinational logic may be in a state that includes a high level of leakage when the clock is gated, thereby resulting in wasted power when the combinational logic is idled.
There is a need to reduce leakage current, whether in a clock gating scenario or otherwise.